Efficient Non-Quasi-Static MOSFET's Model for Circuit Simulation - Electron Devices Meeting, 1995., International

A fast numerical resolution of the Poisson and current continuity equations is used to model non-quasi-static effects in MOS circuits under fast switching conditions. The resulting model is continuous over all regimes of operation and accounts for the non-instantaneous redistribution of the channel charge. The capabilities of this modelling approach are exemplified through the simulation of current mode analog circuits. Introduction Accurate modeling of static currents, conductance and charge dynamics is essential for the design of modern digital and analog circuits. In the analog domain, the shortcomings of many modeling approaches often originate from transistors biased between linear and saturation regimes where discontinuities limit the accuracy and the convergence properties. Moreover, the finite charging/discharging time of the channel may significantly degrade the performances of modern circuit architectures due to charge injection [l]. However, most MOSFET's models reveal poor prediction capabilities for high frequency operations for which quasi-static (QS) operation is often violated. This paper proposes a one-dimensional CAD-oriented model continuous over all operating regimes suitable for long and short channel devices. In addition, the non-quasi-static (NQS) charge redistribution is implicitly accounted for. In comparison with other published NQS models, our approach is not restricted to small signals [2], accounts for velocity saturation [3] and does not require any restrictive assumptions on the partitioning of the channel charge between source and drain [4]. Model formulation The one-dimensional resolution of the Poisson equation is extended beyond the gradual channel approximation to account for short channel effects, velocity saturation and channel length modulation. By applying the Gauss law to a narrow vertical strip in the channel (Fig. l ) , the surface potential can be related to the depletion and inversion charges and to the lateral electric field in the channel direction: Q i (nn) dx, -+ Qd (x,) dx, (1) where Qi and Qd denotes the inversion and depletion charges per unit area, respectively. Assuming that E,(x,y) at position x remains quasi constant in the bulk direction (y-direction) , the above equation is integrated over a distance corresponding to the depletion depth: Finally, a linear finite-difference scheme is used to discretize the resulting equation. This approach is less restrictive than the model proposed in [ 5 ] . A one-dimensional version of the current equation is assumed according to a charge sheet formulation. Special care must be devoted to discretize this equation to correctly account for the exponential relation between the potential and the electron concentration. The final form is given by: where B(x) is the Bernouilli function while others variables have their classical meaning. The current continuity and Poisson equations are consistently solved using a Newton method. In practice, 10 discretization points along the channel proved to be sufficient to achieve a precision comparable to 2D simulation results performed on a dense mesh. The mobility dependences are classically modeled according to 161 and [7]. No empirical parameters are introduced to improve the model accuracy. The model was coded in C and introduced in the ELDO circuit simulator [8] which retains the same functionality than SPICE. I , , , Depletion limit Fig-1: Illustration of the one-dimensional structure and of the discretization scheme 37.4.1 0-7803-2700-4 $4.00 01995 IEEE IEDM 95-945 Results The present model proved to be very efficient in simulating the DC characteristics of short and long channel n-MOSFET's. It was first exercized on a 0.25 pm (L,ff) technology described in [9]. As shown in Fig. 2, a close agreement is obtained with exprimental data and continuous current variations are obtained, in particular, at the limit between linear and saturation regimes. Fig. 3 and Fig. 4 report the drain current and conductance variations with the drain voltage for a 1 pm (Leff) technology [lo]. The largest discrepancy between simulated and measured results is obtained at high VGs and VDS which are not bias conditions of practical relevance in most of analog applications. Fast transient excitations have been applied to the gate (5V/0.5 ns) of relatively long devices (L=5 pm) to enhance the effect of the NQS charge redistribution in the channel. The results are systematically compared to 2D numerical calculations using IMPACT3.3 [ 111 and to simulations performed with BSIM3 using the defaulted 0/100 channel charge partition [12]. Fig. 5 illustrates the charging of the channel through negative source and drain currents in linear operation. Fig. 6 shows the corresponding gate and bulk currents. An excellent agreement is found between our model and 2D physical simulations. In particular, an excellent continuity is obtained when the high state is reached on the gate terminal (t=0.6 ns). Beyond that point a smooth relaxation of currents to their DC values is obtained. In contrast, BSIM3 simulations suffer from unphysical current spikes and overlooks the NQS delay. The accuracy of the model is also demonstrated for a fast turn-off in linear regime in Fig. 7 and 8. Results of switch-on and switch-off in the saturation regime are reported in Fig. 9 and 10, respectively. Circuit applications Fig. 11-a shows, as a first application, a simple pass transistor connected to two capacitances. In this case, the injection of the channel charge on the source drain nodes during tum-off is illustrated. The overlap capacitance are not considered to separate NQS effects from feedthrough currents. Fig. l l-b gives the voltage errors induced on each storage node given by BSIM3 and our model. Fig. 11-c clearly shows that a QS model overtimates the voltage deviation on the smallest capacitance (Gin) due to a poor modeling of transient currents for a gate voltage close to the threshold. Oscillations due to discontinuities of the charge model in BSIM3 are observed on currents when a trapezoidal integration scheme is selected in ELDO. In contrast, the present model does not require the use of a Gear type integration method. The second example concems the simulation of two cascaded current copier cells (Fig. 12-a). In analog signal processing, this kind of architecture is specially attractive because sampled currents rather than voltages are used to represent signals. This offers the advantage of lower supply voltage operation and allows implementation with digital oriented (potentially deep submicron) MOS technologies [ 131. In this circuit, M3 and M6 operate as memory transistors. On phase and $la (Fig. 12-b), the sum of the sample input current Iin and 6.0